Dr. Mehran Goli

Modellierung digitaler Systeme auf Register-Transfer-Ebene (RTL) mit Verilog HDL

• Summer Semester 2022
• Computer Science, University of Bremen

Digital Systems Modeling and Verification using SystemVerilog

• Winter Semester 2021/2022
• Computer Science, University of Bremen

Modellierung digitaler Systeme auf Register-Transfer-Ebene (RTL) mit Verilog HDL

• Summer Semester 2021
• Computer Science, University of Bremen

Digital Systems Modeling using Verilog and SystemVerilog: Design, Test and Synthesis

• Winter Semester 2020/2021
• Computer Science, University of Bremen